FIG. 1 shows a conventional 2T2C ferroelectric random access memory cell 105. The memory cell comprises first and second ferroelectric capacitors 140a and 140b, each having a ferroelectric material, such as lead zirconate titanate (PZT), located between first and second plates. First plates of the capacitors are commonly coupled to a plateline 170 while second plates or the capacitors are coupled to respective bitlines 150a and 150b of a bitline pair via cell transistors 130a and 130b. The gates of the transistors of a memory cell are commonly coupled to a wordline 160. The bitline pair includes additional memory cells, forming a column of memory cells.
A sense amplifier having inverting and non-inverting terminals is coupled to one end of the bitline pair. One bitline (BL) is coupled to the non-inverting terminal of the sense amplifier while the other bitline (/BL) is coupled to the inverting terminal. The other end of the bitlines of the bitline pair is coupled to ground. Each bitline has a biltine capacitance. The bitline capacitance usually originates from parasitic capacitances caused by, for example, wire to wire coupling or junction capacitance. In some applications, a capacitor may be coupled to the bitline to provide the bitline with the desired bitline capacitance value. The capacitor, for example, can be formed by a gate oxide capacitance. The bitline capacitance is needed for the cell capacitor to produce a read signal on the bitline. For a ferroelectric capacitor, the magnitude of the read signal depends on the polarization direction of the ferroelectric material. For example, a first polarization direction produces a read signal equal to a first voltage level (e.g., VLO) while the other direction produces a read signal equal to a second voltage level (e.g., VHI)
The two capacitors of a 2T2C memory cell are always in the opposite state. One bitline will have a read signal equal to VLO and the other VHI when a memory cell is read. The two signals produce a differential read signal (e.g., difference between VLO and VHI). Depending on whether the differential signal is positive or negative, a logic 1 or logic 0 is stored in the cell. By storing the bit of information in opposite states in two capacitors, the two read signals from a cell are compared with each other. This eliminates the need of a reference voltage to perform a read. The absence of a reference voltage, however, makes it difficult to vary the sensing window (e.g., difference between VLO and VHI) for performing signal margin tests during reliability testing of the IC. From the foregoing discussion, it is desirable to provide signal margin test circuit for 2T2C memory ICs.